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Espressif Systems /ESP32-S3 /ASSIST_DEBUG /CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1

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Interpret as CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1

Description

bus busy configuration register

Fields

CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1

non busy cycle,for example: when cycle=100 and cycle=10,it means that in 100 cycle, if busy access success time less than 10, it will trigger interrutpt

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Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data